A chip can be available without an AI model being able to make the most of it. That is what makes the prospect of Google TPUs at OpenAI interesting: beyond a possible purchase, it raises the question of the work required to run the same models across several hardware families.
On 28 October, Decrypt reported a plan by OpenAI to buy TPUs, citing The Information. The article said that the companies had not confirmed the plan and gave no details of the amount, quantity or delivery date. This must remain a reported piece of information; a presumed intention should not be turned into a completed order.
Another piece of information can be consulted directly: OpenAI is looking for an engineer to optimise its models on TPUs. The role describes specific technical work. It does not say who owns the machines, how many will be used or what proportion of services will rely on them.
What a TPU does
A TPU, or “Tensor Processing Unit”, is a specialised circuit designed by Google to accelerate machine-learning calculations. Google Cloud documentation describes, among other things, large operations on matrices, the arrays of numbers used in neural networks.
The benefit is not simply that one chip is faster in absolute terms. Google itself says that the choice between a CPU, GPU and TPU depends on the workload. The operations being performed, how they are organised and memory requirements all matter. A specialised processor is not automatically the best choice for every programme.
For readers, the essential distinction is between the model and the hardware that runs it. The former contains an arrangement of calculations and learned parameters; the latter provides the resources to carry them out. Changing chip supplier does not, by itself, mean replacing ChatGPT with a Google model.
The compiler: an essential link between model and machine
For TPUs, Google explains that code must pass through XLA, a compiler that transforms the model’s operations into instructions suited to the hardware. Some of the programme continues to run on the host machine.
This can be seen as an organisational problem: the same list of calculations can be executed more or less efficiently depending on how they are distributed and how the data moves. The name of the chip is not enough to describe this arrangement. The behaviour of the complete system needs to be measured.
This is precisely the area covered by the “Software Engineer, TPU Compilers” job listing published by OpenAI. The company is looking to improve the execution of its models, identify bottlenecks and work on latency, throughput and hardware utilisation. It also mentions building performance tests and validating the accuracy of results.
This listing is evidence that OpenAI is recruiting for this project. It does not establish a date for a large-scale deployment. A team can prepare, experiment with or improve an architecture without all commercial applications already using it.
Three measures that do not tell the same story about performance
Latency is the waiting time before a result is returned. Throughput indicates how much work can be processed in a given period. Hardware utilisation shows what proportion of its capacity is actually being used. These three dimensions allow different questions to be asked.
For a conversation, one might focus on the time before a reply. For a service handling many requests at the same time, the total quantity processed also matters. A striking figure in a test does not tell the whole story if the type and size of requests, and the conditions under which they are processed, are unknown.
A meaningful comparison should also specify the required quality of the result and the total cost of processing. These are criteria for analysis, not performance figures that we attribute here to an OpenAI system running on TPUs. None of the documents cited provides a public comparison that would quantify the savings from such a purchase.
Broadcom: a separate announcement with its own timeline
OpenAI’s hardware diversification does not rely solely on this press report. In a statement dated 13 October 2025, OpenAI and Broadcom announced a collaboration involving 10 gigawatts of custom accelerators. OpenAI was to design the accelerators and systems, which would be developed and deployed with Broadcom.
The announced timeline targeted the start of deployment in the second half of 2026 and completion by the end of 2029. The partnership includes networking equipment, notably Ethernet. It therefore covers a set of infrastructure, going beyond the processor alone.
The 10 gigawatts describe power associated with the announced programme. They are neither an investment amount nor a volume of responses produced. And a timeline in a statement does not, by itself, prove that every stage has been completed. The published agreement, deliveries and capacity actually in operation must be distinguished.
What would really change with several architectures
The possible strategic benefit is having several options for securing computing capacity. But diversification also means maintaining several technical pathways: running the models, measuring their performance and checking that results continue to meet the service’s requirements.
The job listing makes visible this less spectacular part of the chip race. It shows that the challenge also involves code, measurement tools and day-to-day operations. Announced volumes do not tell us how much work will be required to turn purchased capacity into a useful service.
The developments to come should therefore be read on two levels: commercial confirmations, followed by operational results. Who is supplying what, on what timeline, for which tasks and with what measured performance? This combination will make it possible to assess the significance of diversification. Switching from one chip brand to another is only the beginning of the story.
Illustrative photo: an aisle in a data centre. It does not depict an identified OpenAI or Google facility and does not make it possible to identify the chips being used.
Photo: Brett Sayles — Pexels — Pexels licence.
